The present invention relates to a semiconductor integrated circuit having a phase locked loop (PLL) circuit built therein and an operating method thereof, and particularly to a technology useful in, when a loop filter is on-chipped in particular, reducing variations in the characteristics of the PLL circuit due to variations in the device size of each transistor and reducing increases in both circuit scale and power consumption of the semiconductor integrated circuit.
A phase locked loop (PLL) circuit has heretofore been mounted in a semiconductor integrated circuit. This PLL circuit generates a clock signal for operating a logic circuit such as a large-scale logic integrated circuit or the like.
The following patent documents 1 and 2 respectively have described that in order to on-chip a loop filter of a PLL circuit, a main charge pump circuit and a subsidiary charge pump circuit are coupled between a phase output terminal of a phase comparator and an input terminal of the loop filter. In the PLL circuit described in the following patent document 1, the main charge pump circuit and the subsidiary charge pump carry out charging and discharging operations based on outputs being in-phase to each other in response to a phase output signal of the phase comparator. The output of the subsidiary charge pump circuit is coupled to the input of a voltage-current converter of the loop filter. On the other hand, the output of the main charge pump circuit is coupled to the output of the voltage-current converter of the loop filter. In the PLL described in the following patent document 2, a main charge pump circuit and a subsidiary charge pump circuit perform charging and discharging operations based on outputs being in antiphase to each other in response to a phase output signal of the phase comparator. The output of the main charge pump circuit is coupled to one end of a resistor of the loop filter. On the other hand, the output of the subsidiary charge pump circuit is coupled to the other end of the resistor of the loop filter, and a filter capacitor is coupled between the other end of the resistor and a ground potential.
The following patent document 3 has described that in order to reduce the area of a charge pump PLL circuit, one component of an integrated voltage of a loop filter voltage is subtracted from the total loop filter voltage using a current mirror circuit.
The following patent document 4 has described that in order to bring a loop filter of a phase lock oscillator circuit into highly integrated circuitry for the purpose of its miniaturization, a digital circuit comprised of a counter, a decoder and an updown counter converts a pulse width of a charge signal or a discharge signal outputted from a phase detection circuit into a digital signal, and a D/A convertor converts the digital signal into an analog signal and supplies the analog signal to a voltage controlled oscillator in a manner similar to an analog voltage outputted from the loop filter.